Method for reducing corrosion of metal surfaces during semiconductor processing

ABSTRACT

A semiconductor process exposes metal in anticipation of an additional processing step that includes a deposition of a layer. Between the two processing steps, the exposed metal is exposed to ambient conditions that may include humidity. The effect of the humidity is potentially to cause corrosion of the exposed metal causing a yield loss. In order to withstand the various time periods that may occur between processing steps, an inhibitor is applied to the exposed surface causing the formation of a very thin protective layer on the exposed metal, which greatly inhibits corrosion. This thin protective layer does not cause any problems with the subsequent step because the typical following steps all, by their very nature, remove the protective layer. Thus, the time period between the processing step that exposes the metal and the next step is no longer critical due to the protective layer.

FIELD OF THE INVENTION

This invention relates to semiconductor processing, and moreparticularly, to reducing corrosion of metal surfaces that are exposedduring the processing.

RELATED ART

In the manufacturing of semiconductors, one of the problems has beencorrosion of metal surfaces, especially when the metal is copper. Thisproblem occurs primarily in one of two situations. One situation arisesfrom the copper being deposited into trenches in an interlayerdielectric (ILD) and then subjected to chemical mechanical polishing(CMP). This CMP processing is in preparation for a subsequent ILDdeposition, but this ILD deposition may not be able to be carried outimmediately. Thus, there may be wafers with exposed copper that are inthe ambient conditions of the fabrication facility. In such cases thereis significant humidity. A typical amount of humidity is 40%. In thislevel of humidity, the copper begins corroding and given enough time,the corrosion is sufficient to cause two of the copper lines to beshorted together. One of the techniques to prevent this has been to havequeue time rules that the wafers with the exposed copper can only be inthe ambient conditions for a set amount of time. In practice, however,it is very difficult to keep such rules. The equipment that is used forsubsequent processing may not be available for a variety of reasons,such as maintenance, repair, replacement, or qualification. This alsomay prevent optimum usage of the CMP. Optimum use of the CMP equipmentcan cause a big build-up in the amount of wafers with exposed copper.Such build-up can cause an imbalance on the work in process (WIP) in theline and thus force wafers to be exposed to the ambient for too long.

Similar problems occur during via formation in both copper and aluminum.In the case of vias, a hole is formed in the ILD above the metal layerand thereby the hole exposes a portion of the underlying metal. Exposureto the ambient causes the same corrosion situation. In this case thefailure that is caused is an open instead of a short but the adverseeffect is equally bad for both either a short or an open.

Thus, there is a need for a technique to allow for wafers to be able tohave exposed metal surfaces for longer periods of time prior to the nextstage in processing.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitedby the accompanying figures, in which like references indicate similarelements, and in which:

FIG. 1 is a cross section of a semiconductor device according to anembodiment of the invention at a stage in processing;

FIG. 2 is a cross section of the semiconductor device of FIG. 1 at asubsequent stage in processing;

FIG. 3 is a cross section of the semiconductor device of FIG. 2 at asubsequent stage in processing;

FIG. 4 is a cross section of the semiconductor device of FIG. 3 at asubsequent stage in processing;

FIG. 5 is a cross section of the semiconductor device of FIG. 4 at asubsequent stage in processing;

FIG. 6 is a cross section of the semiconductor device of FIG. 5 at asubsequent stage in processing;

FIG. 7 is a cross section of the semiconductor device of FIG. 6 at asubsequent stage in processing;

FIG. 8 is an apparatus useful in performing one or more of the processesused in the progression of steps shown in FIGS. 1-7.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

In one aspect, a semiconductor process exposes metal in anticipation ofan additional processing step that includes a deposition of a layer.Between the two processing steps, the exposed metal is exposed toambient conditions that may include humidity. The effect of the humidityis potentially to cause corrosion of the exposed metal causing a yieldloss. In order to withstand the various time periods that may occurbetween processing steps, an inhibitor is applied to the exposed surfacecausing the formation of a very thin protective layer on the exposedmetal, which greatly inhibits corrosion. This thin protective layer doesnot cause any problems with the subsequent step because the typicalfollowing steps all, by their very nature, remove the protective layer.Thus, the time period between the processing step that exposes the metaland the next step is no longer critical due to the protective layer.This is better understood as shown in the drawings and described in thefollowing description.

Shown in FIG. 1 is a semiconductor device 10 comprising a semiconductorsubstrate 11, a metal layer 12, an interlayer dielectric (ILD) 14, a viahole in ILD 14 to conductor 12, a protective layer 18, and a corrosioninhibitor 20 in the vapor. Semiconductor substrate 11 may be justsemiconductor material, semiconductor on insulator (SOI), or anotheralternative useful as a substrate in semiconductor manufacturing. Metallayer 12 is preferably copper but may be another metal such as aluminum.Metal layer 12 is shown being immediately over substrate 11 forsimplicity but in practice, there would other features, such astransistors, between substrate 11 and metal layer 12. ILD 14 is anydielectric useful for separating conductor layers. ILDs have generallybeen a form of silicon oxide but are becoming more preferably of a low kmaterial. Protective layer 18 is formed by the application of corrosioninhibitor 20. Corrosion inhibitor 20 is applied in the vapor phase andresults in protective layer 18 as a monolayer of corrosion inhibitor 20bonded to metal layer 12. Inhibitor 20 may also be on ILD 14 but doesnot bond to ILD 14. Inhibitor 20 is a material that bonds to metal andinhibits the passage of moisture when so bonded. The choice of the exactcomposition of inhibitor 20 may be optimized for the particular metalbeing protected. Such inhibitors are commercially available from CortecCorporation of St. Paul, Minn.

Without protective layer 18 and in the presence of moisture, a potentialcan develop that causes corrosion. Protective layer 18 inhibits thiscorrosion so that semiconductor device 10 of FIG. 1 can be exposed totypical ambient conditions with minimal risk of corrosion. Thus, thereis no urgency in bringing semiconductor device 10 to the next step inprocessing. Inhibitor 20 may be applied by any convenient way but shouldbe applied as soon as possible after via 16 exposes conductor 12. Theapplication of inhibitor 20 may be by putting the wafers in a box with asource of inhibitor 20. In such case the source of inhibitor 20 can be apad impregnated with inhibitor 20. Another approach is to applyinhibitor 20 immediately following the etch forming via 16 by directapplication of inhibitor 20 to the wafers being etched. This can beachieved by an etch tool that has inlet for inhibitor 20.

Shown in FIG. 2 is a semiconductor device 10 after a layer 22 isdeposited using plasma. Layer 22 can be variety of barriers. Examples ofsuch barriers includes tantalum, tantalum nitride, or titanium nitride,as well as other barrier materials. In addition a seed layer of coppercan be formed over the barrier layer. Thus layer 22 can be just abarrier layer or a composite of a barrier layer and a copper layer.Tantalum and tantalum nitride are both typically deposited bysputtering, which includes the use of plasma. Immediately prior toperforming the sputter deposition, a preclean using an argon plasma isperformed that has the effect of breaking up protective layer 18.Protective layer 18 is thus a sacrificial layer because it is removedafter it has performed its beneficial function. This preclean is usedfor removing native oxide that is formed on the surface of metalconductor 12 at the bottom via 16. If such a preclean were notnecessary, the sputtering step itself, because it uses plasma and isunder vacuum, may be adequate to break up protective layer 18. After thepreclean, layer 22 is deposited.

Shown in FIG. 3 is semiconductor device 10 after application ofinhibitor 24 that forms protective layer 26 over layer 22. Inhibitor 24can be applied in the manner described for inhibitor 20 in FIG. 1 withan impregnated pad or similar to FIG. 1 as being applied to the wafersreceiving the deposition while still in the deposition tool. Thecomposition of inhibitor may be preferably a somewhat differentcomposition from that of inhibitor, especially if the layer 22 is of adifferent material from that of conductor 12.

Shown in FIG. 4 is semiconductor device 10 after via 16 has been filledby metal layer 28. In the case of layer 22 including a copper seedlayer, metal layer 28 comprises copper. In the case of copper, layer 28is deposited by electroplating which uses electrical pulses for thecopper plating. In such case, layer 26 of FIG. 3 is removed immediatelyupon the application of the first electrical pulse. The electroplatingprocess proceeds normally after such removal of layer 26. In the case oflayer 12 being aluminum, layer 28 could be a via plug material, such astungsten, or simply aluminum. In either case the deposition is precededby a preclean such as that described for the preclean of conductor 12prior to the deposition of layer 22.

Shown in FIG. 5 is a semiconductor device 10 after a chemical mechanicalpolishing (CMP) process particularly applicable to layer 28 being copperor tungsten fill. Layer 28 that fills via 16 thus has an exposed surfacethat is susceptible to corrosion in the presence of moisture present intypical ambient conditions. This situation shown in FIG. 5 ispotentially even more at risk to corrosion than the via situationbecause adjacent lines may be very close together, whereas vias havedepth in addition to the distance that the vias are apart.

Shown in FIG. 6 is semiconductor device 10 after application ofinhibitor 30 to form protective layer 32 on layer 28 and layer 22 thatis exposed. Inhibitor 30 may have a somewhat different composition frominhibitors 20 and 24, depending upon the particular metal type beingprotected.

Shown in FIG. 7 is semiconductor device 10 after formation of layer 34.In the case of layer 28 being copper, layer 34 is an ILD. In the caselayer 28 being a tungsten plug or the like, layer 34 is aluminum. In thecase of layer 34 being an ILD, layer 32 is broken up by the nature ofthe deposition of the ILD, which is a plasma enhanced deposition. In thecase of layer 34 being aluminum, which is deposited by a sputteringprocess, there is a preclean as described for the deposition of layer22.

Additional steps that expose metal use inhibitors in the same manner asappropriate as described for FIGS. 1-7. The use of inhibitors can extendeven to the bond pads if found to have a corrosion problem.

Shown in FIG. 8 is an apparatus 40 comprising a tool 36 useful forprocessing semiconductor device 10 and a vapor corrosion inhibitor (VCI)source that supplies an inhibitor to semiconductor device 10 whilesemiconductor device 10 is present in tool 36. In operation, tool 36performs a particular processing operation on semiconductor device 10that exposes a metal surface. Exemplary processing steps include CMPprocessing, opening a via, and depositing a metal layer such as abarrier layer. Immediately upon completion of the processing step thatexposes metal, the inhibitor from VCI source 38 is released tosemiconductor wafer 10. This allows for minimum time between theprocessing which exposes the metal and the application of the inhibitor.

For a simpler alternative, instead of a tool 36, an enclosure that isimpregnated with the inhibitor can be used. In a simple form, the box issimply lined with a material that is both capable of holding theinhibitor and sufficiently outgassing it to achieve the desiredprotective layer.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present invention as set forthin the claims below. For example, specific examples of situations wheremetal is exposed were explained as benefiting from application of aninhibitor, but other situations that expose metal may also be situationsthat benefit from the application of an inhibitor. Accordingly, thespecification and figures are to be regarded in an illustrative ratherthan a restrictive sense, and all such modifications are intended to beincluded within the scope of present invention.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

1. A method for preventing corrosion of metal surfaces of asemiconductor device during semiconductor processing, comprising:exposing a surface of a metal layer of the semiconductor device;depositing and selectively bonding a sacrificial protective layeroverlying the exposed metal layer surface of the semiconductor device,wherein the sacrificial layer protects the exposed surface fromdeleterious effects until subsequent processing of the semiconductordevice; and subsequent processing of the semiconductor device, whereinthe subsequent processing removes the sacrificial protective layer. 2.The method of claim 1, wherein the semiconductor device includes atleast one of a portion of a semiconductor wafer and a semiconductor die.3. The method of claim 1, wherein the metal layer includes a metalfeature of the semiconductor device.
 4. The method of claim 1, whereinthe exposed surface by itself is subject to deleterious effects inresponse to at least one of a moisture containing ambient and an ambientconducive to causing corrosion.
 5. The method of claim 1, whereinexposing the surface can include at least one of an etching process, achemical mechanical polishing process, a metallization process, and aphoto-imageable develop layer process.
 6. The method of claim 1, whereinthe deleterious effects include corrosion.
 7. The method of claim 1,wherein the deleterious effects include at least one of degradedelectrical performance of the semiconductor device, degradedsemiconductor device reliability effects, and undesired electromigrationeffects.
 8. The method of claim 1, wherein the depositing andselectively bonding includes using a vapor corrosion inhibitor to formthe sacrificial layer on the exposed metal layer surface.
 9. The methodof claim 1, wherein the sacrificial layer includes at least onemonolayer of a vapor corrosion inhibitor.
 10. The method of claim 9,further wherein subsequent processing removes the at least one monolayerof the vapor corrosion inhibitor.
 11. The method of claim 1, wherein thesubsequent processing includes forming another exposed metal layer, saidmethod further comprising: exposing a surface of the another metal layerof the semiconductor device; depositing and selectively bonding anothersacrificial protective layer overlying the another exposed metal layersurface of the semiconductor device, wherein the another sacrificiallayer protects the another exposed surface from deleterious effectsuntil subsequent processing of the semiconductor device; and subsequentprocessing of the semiconductor device, wherein the subsequentprocessing removes the another sacrificial protective layer.
 12. Themethod of claim 1, further wherein the subsequent processing includes adeposition of another layer over the semiconductor device.
 13. A methodfor preventing corrosion of metal surfaces of a semiconductor deviceduring semiconductor processing, comprising: exposing a surface of ametal layer of the semiconductor device; depositing and selectivelybonding a sacrificial protective layer overlying the exposed metal layersurface of the semiconductor device, wherein the sacrificial layerprotects the exposed surface from deleterious effects until subsequentprocessing of the semiconductor device; and subsequent processing of thesemiconductor device, wherein the subsequent processing includesremoving the sacrificial protective layer, re-exposing the metal layerand depositing another layer over the semiconductor device and there-exposed metal layer.
 14. The method of claim 13, wherein thesemiconductor device includes at least one of a portion of asemiconductor wafer and a semiconductor die.
 15. The method of claim 13,wherein the metal layer includes a metal feature of the semiconductordevice.
 16. The method of claim 13, wherein the exposed surface byitself is subject to deleterious effects in response to at least one ofa moisture containing ambient and an ambient conducive to causingcorrosion.
 17. The method of claim 13, wherein exposing the surface caninclude at least one of an etching process, a chemical mechanicalpolishing process, a metallization process, and a photo-imageabledevelop layer process.
 18. The method of claim 13, wherein thedeleterious effects include corrosion.
 19. The method of claim 13,wherein the deleterious effects include at least one of degradedelectrical performance of the semiconductor device, degradedsemiconductor device reliability effects, and undesired electromigrationeffects.
 20. The method of claim 13, wherein the depositing andselectively bonding includes using a vapor corrosion inhibitor to formthe sacrificial layer on the exposed metal layer surface.
 21. Asemiconductor processing apparatus for preventing corrosion of metalsurfaces of a semiconductor device between semiconductor processingsteps, said apparatus comprising: means for exposing a surface of ametal layer of the semiconductor device; and means for depositing andselectively bonding a sacrificial protective layer overlying the exposedmetal layer surface of the semiconductor device, wherein the sacrificiallayer protects the exposed surface from deleterious effects untilsubsequent processing of the semiconductor device.
 22. The apparatus ofclaim 21, wherein said exposing means includes at least one of a meansfor performing an etching process, a chemical mechanical polishingprocess, a metallization process, and a photo-imageable develop layerprocess.
 23. The apparatus of claim 21, wherein said apparatus furthercomprising: means for subsequent processing of the semiconductor device,wherein the subsequent processing removes the sacrificial protectivelayer.
 24. An apparatus for implementing corrosion prevention of exposedmetal surfaces of a semiconductor device between independentsemiconductor processing steps, said apparatus comprising: an enclosurefor receiving the semiconductor device; and means for depositing andselectively bonding a sacrificial protective layer overlying the exposedmetal layer surface of the semiconductor device, wherein the sacrificiallayer protects the exposed surface from deleterious effects untilsubsequent processing of the semiconductor device.
 25. The apparatus ofclaim 24, wherein the depositing and selectively bonding means includesa vapor corrosion inhibitor that forms the sacrificial layer on theexposed metal layer surface.
 26. The apparatus of claim 24, furthercomprising one of an internal vapor corrosion emitter, intregal vaporcorrosion emitter, and an external vapor corrosion emitter, wherein theemitter provides a source of the vapor corrosion inhibitor.
 27. Theapparatus of claim 24, wherein the sacrificial layer includes at leastone monolayer of a vapor corrosion inhibitor.
 28. The apparatus of claim24, wherein subsequent processing includes a removal of the at least onemonolayer of the vapor corrosion inhibitor deposited on the surface. 29.The apparatus of claim 24, wherein the deleterious effects includecorrosion.
 30. The apparatus of claim 24, wherein the deleteriouseffects include at least one of degraded electrical performance of thesemiconductor device, degraded semiconductor device reliability effects,and undesired electromigration effects.